The rising popularity of electronic devices such as mobile applications has created a need for power conservation in integrated circuits. The macro-based dual-VDD structure 100 in FIG. 1a proposed by R. Puri, et al. in a paper entitled “Pushing ASIC Performance in a Power Envelope,” published in pp. 788-793 of DAC, 2003, illustrates a known coarse-grained voltage island architecture with macro-based voltage islands 102. A finer grained voltage island circuits include the voltage island circuit of FIG. 1b as described by Usami et al. in a paper entitled “Low-Power Design Methodology and Applications Utilizing Dual Supply Voltages,” in pp. 123-128 of the Proceedings of the Design Automation Conference, 2000, Asia and South Pacific, 25-28 Jan. 2000, and incorporated by reference herein. Other known voltage island circuits may use the layout scheme shown in FIGS. 1c and 1d and disclosed by Ralf Kakerow in a paper entitled “Low Power Design Methodology for Mobile Communication,” published in pp. 8-13 of entitled “Low Power Design Methodology for Mobile Communication,” published in pp. 8-13 of Computer Design: Proceedings of the 2002 IEEE International Conference On VLSI in Computer and Processors, 2002, and incorporated by reference herein.
However, the designs described above suffer from chip area spacing penalties, in addition to complications in the place and route process. Complications may include dense interconnect and long wire routes, causing antenna violations, capacitive parisitics, and other problem. Restriction in localized and global placement and routing, imposed by known dual voltage designs, impede the iterative IC timing convergence process. The IC timing convergence process, including various stages of placement and routing, has a need for simple manufacture methods that provide a high level of control to the designer. Complications in the place and route may delay time to market and may negatively affect circuit timing convergence.